In many semiconductor applications, semiconductor devices are relatively highly integrated (e.g. the size of semiconductor devices is relatively small). In relatively highly integrated semiconductor devices, an arrangement density may be relatively high. In relatively highly integrated semiconductor devices, critical dimension of a mask pattern may be close to resolution thresholds of optical exposure devices (e.g. an optical light-exposure device).
Optical proximity correction (OPC) may be used to compensate for resolution limitations in a photolithography process. In OPC, a mask pattern for a test may be manufactured as a test pattern. A pattern may be transcribed onto a semiconductor substrate using the mask pattern through photolithography. Etching of the pattern may be performed, such that a semiconductor pattern for a test is manufactured on the substrate.
OPC may be utilized with design rules that are relatively small. However, bridge and/or pinching issues may arise due to OPC limitations, which may result in complications (e.g. a critical yield drop). For example, if a particular OPC can not draw a mask pattern according to a 0.16 μm semiconductor design rule due to photolithography resolution limitations, shrinking (or minimizing) may be performed using a 0.18 μm mask pattern to achieve 0.16 μm dimensions. When shrinking is performed, an off-grid phenomenon may occur.
An off-grid phenomenon may have a negative influence in many OPC applications (e.g. model-based OPC and rule-based OPC). For example, as illustrated in example FIG. 1A, if a mask is designed in a beam spot having a 4 nm size on the basis of a line critical dimension (CD) of 190 nm, a 15 nm off-grid phenomenon occurs at a pitch of 390 nm. However, for example, an off-grid phenomenon may not occur in a pitch between 450 nm and 515 nm.
As illustrated in example FIG. 1B, a graphic design system (GDS) may be divided into several pattern pieces (e.g. pattern piece 1, pattern piece 2, pattern piece 4, pattern piece 5, and/or pattern piece 6) to manufacture a mask pattern 3. The pattern pieces may overlap each other to form mask pattern 3.
Pattern piece 1, pattern piece 2, pattern piece 4, pattern piece 5, and/or pattern piece 6 may have different sizes. If pattern pieces are shrunk, mask pattern 3 may not satisfy a 1 nm grid of a minimum database unit. For example, a CD pattern of 105 nm is shrunk by 90%, the resulting CD pattern will be 94.5 nm. However, in this example, the size of the CD pattern will be randomly either 95 nm or 94 nm, since the size of 94.5 nm can not be drawn. Accordingly, as illustrated in example FIG. 1C, the off-grid phenomenon occurs at highlighted section A and highlighted section B, which may result in an unintended mask pattern.